1. Field of the Invention
The present invention relates to a method of setting process parameter for use in manufacturing a semiconductor integrated circuit. The invention also relates to a method of setting process parameter or design rule, or both the parameter and the rule.
2. Description of the Related Art
Recent years saw a rapid advancement of the technology of manufacturing semiconductor integrated circuits. The technology now manufactures semiconductor integrated circuits with the minimum process size of 0.18 μm. The manufacture of such circuits owes to the remarkable progress of micro-pattern forming techniques including mask process, lithography process and etching process.
In the era when the pattern size was sufficiently large, it was possible to form, on a semiconductor wafer, a pattern that is almost identical to the design pattern. The pattern therefore satisfied the specifications as is demanded. As patterns grow finer and more complex, however, it becomes difficult to form, on semiconductor wafers, patterns that accord with the design patterns. In other words, the patterns formed can hardly satisfy the specifications.
Jpn. Pat. Appln. KOKAI Publication No. 7-175204 proposes a method of optimizing the conditions for the process by optimizing the parameters of the mask process or the lithography process. Jpn. Pat. Appln. KOKAI Publication No. 2000-277426 proposes a method of setting optimal exposure conditions for the basic patterns (i.e., line-and-space (L/S) pattern and isolated pattern) of a device. In this method, the exposure conditions are set in consideration of the mask bias based on optical proximity correction (OPC).
In the methods disclosed in Publication No. 2000-277426, the optical exposure conditions are set in consideration of the mask process and the lithography process only. The changes in size, which take place in the etching process, are not taken into account in the method. In view of this, the method cannot be said to provide desired device patterns. Hence, the conventional techniques described above can hardly serve to manufacture devices of such micro-patterns as is desired.
As indicated above, the changes in size, occurring in the etching process, are not considered in the conventional methods. Consequently, it is difficult for the conventional methods to set appropriate process parameters and to form desirable patterns on semiconductor wafers.
Jpn. Pat. Appln. KOKAI Publication No. 2000-199839 proposes a method that can shorten TAT (Turn Around Time) and reduce chip size. This method performs a sequence of steps. First, the design layout of the previous generation is compacted in accordance with the design rules (D.R.) for providing the design layout of the next generation. Then, mask-data processing (MDP) and lithography simulation are performed, by using the design layout thus compacted. Further, the results of both the mask-data processing and the lithography simulation are fed back to the design rules. This method can determine the design rule from the layout pattern that is similar to the actual device layout. Thus determined, the design rule is free of problems that may actually arise in the manufacture of semiconductor integrated circuits.
A design layout prepared by using the design rule obtained by the method described above cannot always provide chips of desired sizes. If the design rule is mitigated for a pattern that has been found dissatisfactory, design rules are mitigated for any other patterns, too. Then, the chip size will be larger than is desired.
To form the patterns in desired sizes, more types of design rules may be formulated. It is practically impossible, however, to allocate a particular design rule to each pattern. The more design rules, the longer the time required to prepare a design layout, and the more complex the verification achieved by using a design rule checker (D.R.C.).
Unless appropriate design rules are allocated to all patterns to be formed, there may be formed dangerous patterns that fail to satisfy prescribed process latitude. The design rules are closely related to the chip sizes (chip areas). If the design rule is mitigated, the chip area will inevitably increase. It is therefore important to set appropriate design rules in accordance with the relation between the number and types of dangerous patterns, the chip size and design rule.
The number of dangerous patterns and the chip area change, depending on not only the design rule but also process parameters. Even if a specific design rule is applied, the number of dangerous patterns and the chip area will change in accordance with the wavelength of exposure light (λ), the numerical aperture (NA) of the lens, the illumination shape (σ, ε), the phase and transmittance of the photomask, the overlay error, and the like.
It is therefore important to grasp the relation between the chip size, dangerous pattern, design rule and process parameters and apply the relation in preparation of the masks. Hitherto, however, such a relation has not been fully applied to the preparation of masks. Inevitably it has been difficult to set such optimal design rules or process parameters as would reduce the chip size as much as possible.
As pointed out above, the changes in size, which occur in the etching process, have not considered. It is therefore difficult to set appropriate process parameters in the conventional methods. Furthermore, it has been hard to set such design rules or such process parameters as would reduce the chip size to a minimum. To this date it has been difficult to form desired patterns on semiconductor wafers.